1. Field of the Invention
The invention relates to active pixel sensor arrays and, more particularly, to a biasing arrangement for complementary metal oxide semiconductor (CMOS) active pixel sensor arrays.
2. Description of the Related Art
Active pixel sensor (APS) imaging devices are described in U.S. Pat. No. 5,471,515, for example. APS imaging devices include an array of pixel cells, generally arranged in rows and columns. Each pixel cell includes a photodetector (e.g., photodiode) that converts light energy into electric signals. The pixel cell also includes one or more transistors. The transistors typically provide amplification, read-out control, and reset of the photodetector signal, and operate to provide reset signal and a photodetector pixel signal as output signals from the pixel cell.
The architecture of a conventional imaging device with a CMOS APS 2 is illustrated in FIGS. 1 and 2. APS 2 includes a row and column array of pixel cells 4. As illustrated in FIG. 1, array rows are oriented horizontally, and array columns are oriented vertically. The 4×4 array pictured in FIG. 1 is merely illustrative. Typical APS arrays are fabricated as much larger arrays.
Referring more specifically to FIG. 2, a representative three transistor (3T) pixel cell 4 is shown as including a photodiode 6 (PD) and a readout portion which includes a source follower transistor 8 (MD) and a row select transistor 10 (MSEL). Pixel cell 4 has a drain of source follower transistor 8 (MD) connected to voltage line 12 (VAA—PIX—COL,j). The source of the row select transistor 10 (MSEL) is connected to a column line 14 of the cell array to which a load transistor 16 (MLD) also is connected. The load transistor 16 (MLD) acts as a current sink for a bias current IBIAS—PIX. Thus, each pixel 4 includes a source follower arrangement of transistors 8, 10, with the pixel and a common current sink transistor 16 for each array column.
The operation of APS 2 will be described with reference to the timing diagram of FIG. 3. The photodiode 6 is reset by pulsing a reset transistor 18 (MRS) with a reset pulse ΦRS. During the ensuing integration (exposure), the photodiode 6 voltage is decreased by the photo current. After the pre-determined integration period, a row select pulse ΦSEL turns ON and an output signal appears at the node denoted by VOUT (FIG. 2).
The output signal voltage is given by Equation 1, as follows:VOUT,sig=AV·(VRS,pix−ΔVsig−(Vth−δVth))  (1)where AV, Vth, VRS,pix and ΔVsig are the voltage gain (AV) and the threshold voltage (Vth) of the source follower, the initial photodiode voltage (VRS,pix) just after the reset, and the voltage swing (drop) (ΔVsig) caused by the accumulation of the signal electrons on the photodiode, respectively.
Vth represents a deviation of the effective threshold voltage, which gives rise to fixed pattern noise (FPN) in the array. FPN (also called nonuniformity) is spatial variation in pixel output values under uniform illumination due to device and interconnect parameter variations (mismatches) across the sensor. It is fixed for a given sensor, but varies from sensor to sensor. FPN increases with illumination, but causes more degradation in image quality at low illumination. CMOS (APS) sensors have higher FPN than charge-coupled devices (CCDs) and suffer from column FPN, which may appear as shadow stripes in the image and can result in image quality degradation.
The output signal voltage VOUT,sig for a column pixel is sampled and held on a first capacitor in a sample and hold (S/H) circuit 20 (FIG. 1). Then the photodiode is reset again, and the output reset voltage is sampled and held on a second capacitor in sample and hold (S/H) circuit 20.
The output reset voltage is given by Equation 2, as follows:VOUT,rs=AV·(VRS,pix−(Vth−δVth  (2)The signal voltage swing, representing the light-induced signal on the photodiode, can be extracted by subtracting (1) from (2), which yields:VSIG=AV·ΔVsig  (3)Thus, variations in VRS,pix and Vth are eliminated, in principle.
Referring again to FIG. 1, a row select circuit 22 selects a row to be reset or readout. All rows are selected for read out in sequential fashion. The S/H circuit 20 performs sample and hold operations for the reset and pixel signals for each of the array columns, which are represented by equations (1) and (2). The outputs of the S/H block 20 are fed to a differential amplifier which subtracts the two signals to produce VSIG in accordance with equation (3). This signal is then digitalized and sent to an image processor with other signals from the pixels of array 2.
The FIG. 3 pulse timing diagram illustrates the operation of the image sensor shown in FIG. 1 having photodiode active pixels. Conventionally, the row select and sample-and-hold operations are performed in a row-by-row fashion, represented in FIG. 3 by these successive rows i−1, i, and i+1. A period at the start of each frame between the end of the last row select and the beginning of the first row select is called the vertical blanking period (V_BL).
In a large format array based on the representative architecture shown in FIG. 1, a problem occurs due to the voltage (I-R) drop along the VSS line, which couples ground to all the column circuit sink transistors 16 as illustrated in FIG. 4. During the readout period, voltage drops along the VSS line, which is typically grounded at terminal AVss, cannot maintain the established (ground) level for each column line due to parasitic resistances RSS denoted in FIG. 4. The graph of FIG. 5 illustrates the voltages on column lines 1 to jmax as shown, those column lines farthest from terminal AVss have a voltage above ground while those closest to AVss have voltages at or near ground along the line VSS.
The voltage drops along the line Vss impact the bias currents IBIAS—PIX produced by column line transistors 16. The bias current is given by Equation (4), as follows:IBIAS—PIX,j=β/2·(VGS,j−VTH)2=β/2·(VLN−VSS—PIX—COL,j−VTH)2  (4)where β, VGS,i, and VSS—PIX—COL,j are a process and size dependent parameter (β), the gate-source voltage for the j-th load transistor (VGS,i), and the VSS voltage at the column J (VSS—PIX—COL,j), respectively. Thus, as VSS—PIX—COL,j becomes higher than VSS, the bias current decreases. The change in the output voltage due to the higher VSS is given approximately by Equation (5) as follows:
                              Δ          ⁢                                          ⁢                      V            OUT                          =                                                                              β                  LD                                                  β                  D                                                      ·            Δ                    ⁢                                          ⁢                      V            SS                                              (        5        )            where βLD, βPD, VSS are β for MLD and MD, and the voltage change on the VSS line, respectively. If a fixed pattern noise (FPN) suppression operation, where the signal voltage swing is extracted by subtracting Eq. 1 from Eq. 2, is not performed, shading appears in a reproduced image. By applying such an FPN suppression operation, shading caused by the voltage change on VSS line, expressed by Eq. 5, may be suppressed. However, other shading will still be present.
Shading may be caused, for example, by decreased bias currents due to the reduced effective gate-source voltage VGS of the load transistor 16 (MLD), which may result in variations in time constants for charging and discharging the sample and hold capacitors CSHS or CSHR within the sample and hold circuit 20. The capacitor CSHS and CSHR respectively sample and hold the pixel output signal and reset output signal. The time constants are given approximately by Equation 6, as follows:
                                                        τ              =                            ⁢                                                C                  SHX                                                  g                  m                                                                                                        =                            ⁢                                                C                  SHX                                                                      2                    ·                    β                    ·                                          I                      BIAS_PIX                                                                                                                              (        6        )            Thus, the resulting voltages on the sample and hold capacitors may change when the pulse width of the sample-and-hold pulse is comparable to the time constant. The pulse width of the sample-and-hold pulse may be comparable to the time constant since higher resolution image sensors require shorter pulse widths to obtain a given frame rate. Another related concern is the source follower gain variation due to the decreased bias current.
Similar voltage drops occur along a voltage line 24 which supplies the pixel voltage VAA—PIX, as a result of parasitic resistances RAA along that line, as shown in FIG. 4. The voltage changes here affect the pixel output voltage little, however, since the driver transistor 8 (MD) of each pixel cell (FIG. 2) operates in the saturation region and thus the drain voltage does not affect its drain current. A problem arises, however, during the reset operation.
There are two modes of pixel reset operation, “hard” and “soft.” A “hard reset” refers to a reset where the reset transistor 18 (MRS) operates in its linear region. The initial voltage of the photodiode VRS,pix is given by Equation 7, as follows:VRS,pix=VAA—PIX—COL  (7)
To make reset transistor 18 (MRS) operate in its linear region, a pulse height of the reset pulse ΦRS should be higher than VAA—PIX—COL by Vth, where Vth is the effective threshold voltage of the reset transistor 18. Noise associated with the ‘hard’ reset is given approximately by Equation 8, as follows:vhard2=kT/CPD  (8)where k is the Boltzmann's constant, T the absolute temperature in K and CPD is the capacitance of photodiode 6, respectively.
A “soft reset” refers to a reset where the reset transistor 18 (MRS) operates first in its saturation region, and then in the sub-threshold region. An initial voltage VRS,pix of photodiode 6 is given by Equation 9, assuming the pulse height of the reset pulse ΦRS is equal to VAA—PIX, as follows:VRS,pix=VAA—PIX—−Vth  (9)
When the pulse height of the reset pulse ΦRS is equal to VAA—PIX, reset transistor 18 (MRS) operates in its saturation region. The final stage at the reset operation is dominated by the sub-threshold operation. Reset noise associated with the ‘soft’ reset is given approximately by Equation 10, as follows:vsoft2=kT/2CPD  (10)
Although the noise associated with the soft reset is less than that associated with the hard reset, there are other concerns with the soft reset. For example, the soft reset yields non-linearity in low light level photo-conversion characteristics of the pixel cell. The soft reset also yields image lag due to the fact that the final stage at the reset operation is dominated by the sub-threshold operation of the reset transistor 18. Therefore, the hard reset is preferable to the soft reset, especially for motion picture applications, for example.
In order to perform the hard reset, the pulse height of the reset pulse ΦRS should be higher than VAA—PIX—COL by Vth, which requires an additional voltage pump circuit in a row select pulse generation circuit (assuming that VAA—PIX is the highest voltage supplied to the image sensor.) There may be a case, however, in which the soft reset is applicable when noise performance and dynamic range are the most important performance parameters.
If a large format array is built based on the architecture shown in FIG. 1, a problem associated with the hard reset occurs due to the voltage (I·R) drops along the VAA—PIX line. When a row is selected for readout, the pixel bias currents Ibias-pix flow from VAA—PIX to AVSS as shown in FIG. 4. During this row select period, voltages along the VAA—PIX line cannot maintain an appropriate level, as shown in FIG. 6, due to parasitic resistances RAA along the VAA—PIX line.
The pixel reset ΦRS is applied after the signal voltage sampling (ΦSHS=‘H’) while the row select pulse ΦSEL is kept on, as shown in the timing diagram of FIG. 3. Since the pixel reset voltage, which is a drain voltage of MRS, is VAA—PIX, as expressed by Eq. 7, the initialized voltage of each photodiode VRS,pix on a row is not identical, as shown in FIG. 6. In addition, if the VAA—PIX line is contaminated by noise, that noise is sampled on a photodiode.